A clock shifter is an electronic circuit that level-shifts an input clock signal from a first voltage domain to a higher (or lower) second voltage domain output clock signal. Clock shifters have been manufactured using a pair of cross-coupled transistor switches with a corresponding pair of coupling capacitors connected between each transistor source and a true or complement version of an input clock signal. An output node of the shifter circuit is tied to a series switch, which controls voltage boosting for the circuit to generate the second voltage domain output clock.
A conventional clock shifter circuit is described in U.S. Pat. No. 6,118,326, assigned to Analog Devices, Inc., the assignee of the present invention. This clock shifter circuit receives a high-current supply voltage in order to level-shift an input clock signal. The high-current supply voltage boosts a voltage level of an output node for the shifter circuit to above the supply voltage level to activate the transistor switches. The circuit employs a series-coupled output switch in order to boost the output node voltage level to greater than the supply voltage for activating the transistor switches.
A need in the art exists to supplement the above described shifter circuit to improve clock shifting performance.